1. Field of the Invention
The present invention relates to an emulator system in a microcomputer system.
2. Description of Related Art
A conventional emulator system generally emulates using two microcomputer chips, that is, a CPU emulation chip and a peripheral emulation chip: The CPU emulation chip has a bus master function of the CPU, DMAC and the like, that is, the function of accessing the memory and executing instructions read therefrom; and the peripheral emulation chip executes peripheral functions of a timer, serial I/Os, A/D converters or the like.
The CPU emulation chip inputs and outputs all the bits of its address bus and data bus, signals on its control bus such as read/write signals, emulation signals, and signals required for interface with the peripheral emulation chip.
On the other hand, the peripheral emulation chip inputs and outputs the lower bits (eight bits in this case) of its address bus, all the bits of the data bus, signals on its control bus such as read/write signals, and signals required for interface with the CPU emulation chip.
The CPU emulation chip can be implemented either by way of the mode setting of a volume production chip or by developing a dedicated chip. This is because developing the dedicated chips does not become a great burden because one type of CPU emulation chips can fulfill all the requirements of each series of microcomputers.
In contrast with this, a particular type of peripheral emulation chips is required for each type of microcomputers. Hence, developing dedicated peripheral emulation chips becomes a great burden and difficult to implement. Thus, the peripheral emulation chip can be more effectively implemented by way of the mode setting of volume production chips.
FIG. 7 is a schematic block diagram of a conventional emulator system. In FIG. 7, the reference numeral 101 designates a CPU emulation chip which inputs and outputs a 20-bit signal on its address bus, a 16-bit signal on its data bus, control signals on its control bus, emulation signals, and signals required for interface with a peripheral emulation chip.
The reference numeral 102 designates a peripheral emulation chip which inputs and outputs a lower 8-bit signal on its address bus, a 16-bit signal on its data bus, control signals on its control bus, and signals required for interface with the CPU emulation chip 101. The ports P0, P1, P2 and P3 of the peripheral emulation chip 102 are connected to the lower eight bits of its address bus, lower eight bits of its data bus, upper eight bits of the data bus, and its control bus, respectively. The sum total of the 8-bit ports P0, P1, P2, P3 and P4 are 40.
The reference numeral 103 designates a port emulation gate array which emulates the functions of the 8-bit ports P0, P1, P2 and P3, and inputs and outputs signals needed for the emulation such as the signal on the lower 8-bits of the address bus, the signal on the 16-bit data bus, and the control signals on the control bus.
The reference numeral 104 designates an emulator body which includes a memory 108 for storing instructions executed by the CPU emulation chip 101, and carries out the overall control. The emulator body 104 inputs and outputs signals needed for the emulation such as the signal on the 20-bit address bus, the signal on the 16-bit data bus, and the control signals on the control bus.
The reference numeral 105 designates the address bus, 106 designates the data bus, and 107 designates the control bus for carrying control signals such as read/write signals. The ports P0-P3 of the port emulation gate array 103 and the port P4 of the peripheral emulation chip 102 are connected to a user board.
FIG. 8 is a block diagram of the peripheral emulation chip 102. In FIG. 8, the reference numeral 121 designates a mode setting circuit for outputting a mode signal designating a peripheral emulation mode or a normal mode. The mode signal is placed at a "0" level in the normal mode, and a "1" level in the peripheral emulation mode. The reference numeral 122 designates a core block for controlling the 20-bit address bus A0-A19, 16-bit data bus DB0-DB15, and control bus CSP, BHE, RD and WR.
The core block 122 includes a block functioning as a bus master such as a CPU and DMAC. The core block 122, receiving the mode signal, operates as an ordinary CPU or DMAC, and controls the address bus, data bus and control bus if the mode signal designates the normal mode. However, if the mode signal designates the peripheral emulation mode, it disables the CPU and DMAC, and causes those buses to be floating (high impedance).
The reference numerals 123, 124 and 125 each designate a peripheral function block for executing peripheral functions such as a timer, serial I/O, A/D converter, or the like. The peripheral function block 123 comprises a special function register 136 and a peripheral function block body 137, both of which are connected to the address bus, data bus and control bus. When the peripheral function block 123 operates as a serial I/O, the special function register 136 functions as a register for selecting a communication rate and for storing communication data, and the peripheral function block body 137 functions as the main body of the serial I/O.
The reference numerals 126, 128, 130, 132 and 134 designate port P0 circuit, port P1 circuit, port P2 circuit, port P3 circuit, and port P4 circuit, respectively, with which the address bus, data bus and control bus are connected. The reference numerals 127, 129, 131, 133 and 135 each designate a selector having terminals a, b, s and x. The mode signal is connected to the terminal s of each of the selectors 127, 129, 131 and 133 so that each of the selectors connect its terminal a with the terminal x when the mode signal is placed at the "0"0 level (in the normal mode), whereas connect its terminal b with the terminal x when the mode signal is placed at the "1" level (in the peripheral emulation mode). The terminal s of the selector 135 is connected to an output of the special function register 136.
The selector 127 has its terminal x connected to external pins P00-P07, its terminal a to the port P0 circuit 126, and its terminal b to the address bus A0-A7. The selector 129 has its terminal x connected to external pins P10-P17, its terminal a to the port P1 circuit 128, and its terminal b to the lower bits DB0-DB7 of the data bus.
The selector 131 has its terminal x connected to external pins P20-P27, its terminal a to the port P2 circuit 130, and its terminal b to the upper bits DB8-DB15 of the data bus. The selector 133 has its terminal x connected to external pins P30-P37, its terminal a to the port P3 circuit 132, and its terminal b to the control bus. The selector 135 has its terminal x connected to external pins P40-P47, its terminal a to the port P4 circuit 134, and its terminal b to the peripheral function block 123. Here, the external pins P00-P07, P10-P17, P20-P27, P30-P30 and P40-P47 correspond to the port P0, P1, P2, P3 and P4 of FIG. 1, respectively.
The reference numeral 138 designates a ROM which is connected to the address bus, data bus and control bus, and stores instruction codes executed by the CPU in the core block 122. The ROM 138 is also connected to the mode signal which enables it in the normal mode and disables it in the peripheral emulation mode, in which case the address bus, data bus and control bus are made floating.
The reference numeral 139 designates a RAM which is connected to the address bus, data bus and control bus. The RAM 139 is also connected to the mode signal which enables it in the normal mode and disables it in the peripheral emulation mode, in which case the address bus, data bus and control bus are made floating.
Next, the operation of the conventional emulator system will be described.
When the mode setting circuit 121 designates the normal mode, the core block 122, ROM 138 and RAM 139 are all enabled. In addition, since the selectors 127, 129, 131 and 133 each have their terminals x connected to their terminals a, the external pins P00-P07 are connected with the port P0 circuit 126, the external pins P10-P17 are connected with the port P1 circuit 128, the external pins P20-P27 are connected with the port P2 circuit 130, and the external pins P30-P37 are connected with the port P3 circuit 132 so that they can achieve their functions.
Furthermore, the CPU in the core block 122 can read the instructions from the ROM 138 to execute them. When using the peripheral function block 123, the CPU controls the address bus, data bus and control bus, and reads from or writes in the special function register 136 necessary data, thereby establishing the state for using the peripheral function block 123. For example, when the CPU in the core block 122 uses the peripheral function block 123 as a serial I/O for communicating with the outside, the CPU sets the special function register 136 to have the selector 135 connect its terminals b and x. This enables the external pins P40-P47 to be used as the external pins of the serial I/O, thus making the communication possible.
Moreover, controlling the address bus, data bus and control bus, the CPU in the core block 122 can access to the RAM 139, port P0 circuit 126, port P1 circuit 128, port P2 circuit 130, port P3 circuit 132, port P4 circuit 134, and peripheral function blocks 124 and 125.
On the other hand, when the mode setting circuit 121 designates the peripheral emulation mode, the core block 122, ROM 138 and RAM 139 are disabled, and the address bus, data bus and control bus are made floating. In addition, since the mode signal designates the peripheral emulation mode, the selectors 127, 129, 131 and 133 connect the external pins P00-P07 with the address bus A0-A7, the external pins P10-P17 with the data bus DB0-DB7, the external pins P20-P27 with the data bus DB8-DB15, and the external pins P30-P37 with the control bus, respectively.
Thus, the peripheral function blocks 123, 124 and 125 become accessible through the external pins P00-P07, P10-P17, P20-P27 and P30-P37.
The operation in the emulation will now be described with reference to FIGS. 7 and 8. The CPU emulation chip 101, controlling the address bus, data bus and control bus, accesses the memory 108 in the emulator body 104, reads the instruction codes therefrom, and executes the instructions.
Since the mode setting circuit 121 of the peripheral emulation chip 102 designates the peripheral emulation mode in this case, the CPU emulation chip 101 can access to the peripheral function blocks 123, 124 and 125 through the external pins P00-P07, P10-P17, P20-P27 and P30-P37, that is, the port P0, P1, P2 and P3.
For example, when the CPU emulation chip 101 tries to communicate with the outside via the peripheral function block 123 functioning as the serial I/O, it sets the special function register 136 in the peripheral emulation chip 102 such that the external pins P40-P47 of the peripheral emulation chip 102 function as the external pins of the serial I/O, thereby making the communications possible through the port P4.
However, the peripheral emulation chip 102 cannot provide the ports P0, P1, P2 and P3 with the functions of the terminals of the peripheral function blocks because the corresponding external pins P00-P07, P10-P17, P20-P27 and P30-P37 of the peripheral emulation chip 102 are connected to the address bus, lower and upper data bus and control bus, respectively, but cannot be connected to any of the peripheral function blocks.
In view of this, the functions of the ports P0, P1, P2 and P3 are implemented by the port emulation gate array 103. The port emulation gate array 103 have the equivalent functions as those of the port P0 circuit 126, port P1 circuit 128, port P2 circuit 130 and port P3 circuit 132 of the peripheral emulation chip 102. Thus, the CPU emulation chip 101 must access the port emulation gate array 103 when using these ports.
With the foregoing configuration, the conventional emulator system has a problem in that its peripheral emulation chip has its most of its external pins occupied by the address bus, data bus and control bus in the peripheral emulation mode. Accordingly, these external pins cannot implement the port functions of the peripheral function block such as the input/output pins of the serial I/O. Besides, the gate array is required which executes the port functions in behalf of the peripheral emulation chip in the emulator system.